Integrated circuit including bypass signal path

ABSTRACT

An integrated circuit includes a bypass signal path exchanging, between transceivers which are included in the integrated circuit, a signal transmitted/received between a transceiver of the transceivers and an internal logic circuit which processes data being input/output by transceiver with bypassing the internal logic circuit, a switch switching a pathway of the bypass signal path, and a switch changeover controller transferring a switch control signal that performs a changeover of the switch.

FIELD

The embodiments discussed herein are related to an integrated circuit.

BACKGROUND

In recent years, the performance of components constituting a computerand other information processing apparatuses has been improvedsignificantly. This seems to be due particularly to the improvement inthe component performance of SRAM (Static Random Access Memory), DRAM(Dynamic Random Access Memory), processors, switch LSI (Large ScaleIntegration), and so on. However, in order to improve systemperformance, the signal transmission speed between these components andelements needs to be improved. In this regard, the improvement of systemperformance includes an increase in the transmission capacity that ismeasured by bit/sec, a decrease in the transmission delay, and so on.

For example, the gap between the speed of memories such as SRAM, DRAMand that of a processor is expanding, and the gap between the speeds ishindering the improvement of computer performance. In addition, as ICchips become larger, not only the signal transmission between thesechips but also the signal transmission speed between elements andbetween circuit blocks on an IC chip is becoming a significant factorthat limits the performance of the IC chip. Furthermore, the signaltransmission speed needs to be improved also for the coupling betweenservers or between boards.

However, with an improvement in the signal transmission speed, in a casewhere a signal is received at a high data rate on a printed circuitboard on which a plurality of IC chips are mounted, the signal qualitydeteriorates to a large extent, due to signal reflection and crosstalk.In addition, in a case where a plurality of IC chips are mounted on acircuit board and signal lines coupling between the IC chips cross in acomplicated way, and with some signals, where a plurality of IC chipsare coupled to one signal line, the signal quality deteriorates to alarge extent.

The wiring diagram in FIG. 18 includes IC chips 181-184 (IC1-IC4). It isa configuration example of so called multidrop coupling where IC chipsare coupled by signal lines.

Such a wiring of signal lines causes the deterioration of signal quality(distortion of waveform), due to mutual interference between a pluralityof signals and multiple reflection of a signal caused by impedancemismatching at a multidrop coupling point.

Therefore, proposals have been made for avoiding the degradation of thesignal quality due to the wiring topology having complicated crossingand multidrop coupling. In Japanese Laid-open Patent Publication No.4-282913, a proposal is made to make it possible to perform signaltransmission with little delay, by providing a switch for bypassing anLSI and using the bypass path when there is no need to go through theLSI.

In addition, the switching of signals in a general IC chip is performedwith the router function that is built in the signal processing part ofthe IC chip itself. The router function is realized by a logic circuit.In recent years, with the speeding up of the I/O, the operatingfrequency of the logic circuit is often a low value being a fraction(for example, ¼, ⅛, 1/16) of the clock frequency of a signal. Therefore,the router function by means of a logic circuit generates a large signaldelay. For this reason, there has been a problem that when all signalsare routed through the router function and the logic circuit within achip, the overall performance of a system deteriorates due to the signaldelay.

SUMMARY

According to an aspect of the embodiments, an integrated circuitincludes a bypass signal path exchanging, between transceivers which areincluded in the integrated circuit, a signal transmitted/receivedbetween a transceiver of the transceivers and an internal logic circuitwhich processes data being input/output by transceiver with bypassingthe internal logic circuit, a switch switching a pathway of the bypasssignal path, and a switch changeover controller transferring a switchcontrol signal that performs a changeover of the switch.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram illustrating a principle of an embodiment of thepresent invention.

FIG. 2 is a diagram illustrating a principle of an embodiment of FIG. 1of the present invention.

FIG. 3 is a diagram illustrating a configuration of a high-speed I/O,the data rate of the high-speed I/O being 2.5 (Gbit/sec) and the clockfrequency of the internal logic circuit being 2.5 GHz.

FIG. 4A is a diagram illustrating a configuration of a switch.

FIG. 4B is a diagram illustrating a configuration of a switch.

FIG. 5 is a diagram illustrating the control flow of embodiment 1.

FIG. 6 is a diagram illustrating a configuration of a high-speed I/O,the data rate per a signal line of the transceiver being 6.4 (Gbit/sec)while the internal logic circuit is operating with a low clock frequencyof 400 (MHz).

FIG. 7 is a diagram illustrating a configuration using a clock recoverycircuit.

FIG. 8 is a diagram illustrating a circuit including, in its bypasssignal path, a circuit for correcting a timing mismatch (skew) between aplurality of signal lines.

FIG. 9 is a diagram illustrating a configuration of a timing correctioncircuit 85.

FIG. 10 is a diagram illustrating the operation of the timing correctioncircuit 85.

FIG. 11 is a diagram illustrating a configuration in which a currentmode signal transmission circuit with a small amplitude is used for thedata path of the bypass signal path (including a switch).

FIG. 12 is an example illustrating a configuration in which the similarsignal is transmitted to a plurality of destinations by one-to-manycoupling.

FIG. 13 is an example illustrating a configuration in which the delayamount is different respectively for each signal path of the bypasssignal path.

FIG. 14 is a diagram illustrating the control flow of the configurationillustrated in FIG. 13.

FIG. 15 is a diagram illustrating a configuration to which a redundantcircuit is added.

FIG. 16 is a diagram illustrating the control flow of the configurationillustrated in FIG. 15.

FIG. 17 is a diagram illustrating a configuration without a switchcontrol signal path, in which a configuration setting command istransmitted/received via the bypass signal path.

FIG. 18 is a diagram illustrating a conventional example.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments will be explained in detail with reference tothe accompanying drawings.

(Explanation of the Principle)

In order to avoid the degradation of signal quality due to the wiringtopology having a plurality of crossings and multidrop coupling, thetopology is made with a plurality of IC tips coupled by one-to-onewiring without any crossing part of signal lines. Then, in order toexclude crossed wiring and multidrop wiring on the circuit board,input/output signals are switched within the IC chip.

FIG. 1 and FIG. 2 are diagrams illustrating the principle of theembodiment. The circuit illustrated in FIG. 1 includes IC chips 1-4, inwhich IC chips 181-184 illustrated in FIG. 18 (conventional) areprovided and low-latency switches 9-12 are used for the wiring betweenrespective internal logic circuits 5-8.

Here, the switches 9-12 have a function to transmit data selectively toa certain destination, and are capable of performing multiple groups ofdata transmission at the similar time. In addition, assuming no internalconfliction, the time from receiving a frame at an input port tooutputting it through an output port is short in the low-latencyswitches 9-12.

Here, for example, a crossbar switch is used as the low-latency switch.

Next, the crossing parts in the wiring illustrated in FIG. 18(conventional) are all taken inside the IC chips 1-4, and all lines arecontrolled, by the switches 9-12, to be coupled one-to-one. In addition,in a case of transmitting a signal beyond immediately adjacent IC chips1-4, the signal is transferred hopping a plurality IC chips. Thefunction realizes the crossing of the lines and multidrop couplingeffectively.

Meanwhile, FIG. 2 is a diagram illustrating an integrated circuit havinga plurality of high-speed I/O transceivers (transmitter and receiver). Acircuit 21 illustrated in FIG. 2 includes an internal logic circuit 22(data processor), demultiplexers 23, 25, a switch 24, multiplexers 26,27, a bypass signal path 28, and a switch control signal path 29.

The internal logic circuit 22 determines the pathway of the bypasssignal path 28. A signal that may not need switching by the internalrouter logic (the one that may not need any path change once the systemconfiguration is determined) is passed through a low-latency path. Inthis case, the setting of the switch 24 is changed through the switchcontrol signal path 29, on the basis of the result of the calculation ofthe path selection performed in the switch changeover controllerprovided in the internal logic circuit 22. At this time, once the pathis selected at the beginning, few path changes may be required afterthat, and the delay of the internal logic circuit 22 does not matter.

The bypass signal path 28 couples, to another high-speed I/Otransmitter, a signal that a high-speed I/O receiver received fromoutside, bypassing the internal logic circuit 22. The delay in thesignal transmission performed while hopping IC chips is reduced bydisposing the switch 24 that switches the coupling destination to thebypass signal path 28. All signal couplings may be one-to-one with nodelay problem, for a signal that merely goes through IC chips and maynot require any internal logic processing.

Here, the front end part of the transceiver that directly transmits andreceives a high-speed signal is located in the part that directlycouples to the input/output terminal. The high-speed I/O transceiverincludes, not only the front end parts that operates at the highestspeed, but also the multiplexer and demultiplexer located in thesubsequent stage. In FIG. 2, since the switch 24 is located between thecoupled multiplexer and demultiplexer, the switch is integrated into thetransceiver and the receiver.

For the switching timing of the switch, with respect to the low-latencypath, the changeover of the switch may be required to be completedbefore a signal runs. For this reason, the configuration (which signalis to be coupled to where, which signal is to be transmitted bypassingthe integrated circuit and which signal goes through the internal routerlogic) is determined upon starting up the system (that may include aplurality of integrated circuits coupled by the high-speed I/O accordingto the embodiment).

In that case, a data format that may distinguish normal data and settingcommands for configuration may be required. For example, with the dataformat, a special code (for example, Command pattern) assigned for thepurpose of system control may be transmitted for recognizing non-data.

As described above, the high-speed signal lines on the board may becoupled one-to-one, and the propagation delay of the signal hopping viathe chip may also be minimized.

In addition, since the signal lines are couple done-to-one, multiplesignal reflection due to multidrop coupling does not occur.

Furthermore, since there is no signal crossing part, the problems ofcrosstalk and impedance mismatching are reduced, and the transmissionrate may be improved while avoiding the problem of the degradation ofsignal quality, improving the overall system performance.

(Embodiment 1)

FIG. 3 is a diagram illustrating a configuration of a high-speed I/O,the data rate of the high-speed I/O being 2.5 (Gbit/sec) and the clockfrequency of the internal logic circuit being 2.5 GHz. The configurationin FIG. 3 is made with no multiplexer and demultiplexer. The circuit isconfigured for a case such as the one in which the clock frequency ofthe internal logic circuit exceeds several GHz.

An IC chip 31 illustrated in FIG. 3 includes an internal logic circuit32, high-speed I/O transceivers 33, switches 34, switch control signalpaths 35 and a bypass signal path 36.

The four-channel transceiver 33 has eight pairs of I/O ports thatrespectively include four pairs of high-speed I/O transceivers of whichdata rate is 2.5 (Gbit/sec). The transceiver in the I/O port performsthe exchange of signals with the internal logic circuit 32 of whichoperating frequency is 2.5 (GHz). A signal received by the high-speedI/O transceiver 33 is transmitted to the internal logic circuit 32, andthe data in the internal logic circuit 32 is transmitted to outside bythe high-speed I/O transceiver 33. The signal from the high-speedtransceiver 33 is coupled to other high-speed transceivers 33 (includingits own port) via the bypass signal path 36 and the switch 34, bypassingthe internal logic circuit 32.

Any pair of the total eight ports of the high-speed I/O may be coupledvia the bypass signal path 36 and the switches 34. The configurationsuch as the crosspoint type may be used for the switch 34. Thecrosspoint type using eight 8:1 selectors is adopted in the presentexample.

Here, the configuration of the switch is illustrated in FIG. 4. FIG. 4Ais a diagram illustrating a differential-type switch. Input signals D1,DX1 and input signals D2, DX2 are selected by a selector control signalSEL. The selector control signal is input to each switch 34 via a switchcontrol signal path.

The input signals D1, DX1 side is input to a differential input unitincluding transistors Tr1 and Tr2. The input signal D1 is input to thegate of Tr1, and the input signal DX1 is input to the gate of Tr2. Thesource of Tr1 is coupled to a power VDD via a resistor R1. The source ofTr2 is coupled to the power VDD via a resistor R2. The source of atransistor Tr5 is coupled to a ground GND. Meanwhile the respectivedrains of Tr 1, 2, 5 are coupled. The selector control signal is inputfrom the gate of Tr5.

The input signals D2, DX2 side is input to a differential input unitincluding transistors Tr3 and Tr4. The input signal D2 is input to thegate of Tr3, and the input signal DX2 is input to the gate of Tr4. Thesource of Tr3 is coupled to a power VDD via a resistor R1. The source ofTr4 is coupled to the power VDD via a resistor R2. The source of atransistor Tr6 is coupled to a ground GND. Meanwhile, the drains of Trs3, 4, 6 are coupled. The selector control signal is input from the gateof Tr6 via an inverter INV1.

In other words, the conduction of Tr5 and Tr6 is controlled by switchingthe selector control signal. The control in this way enables theswitching of signals output to output VOUT1 and output VOUTX1.

FIG. 4B is a variation of the circuit in FIG. 4A, in which a transistorTr7 is inserted between Tr5, Tr6 and the ground GND to add a bias signal(BIAS).

Next, a control flow illustrated in FIG. 5 is explained.

In step S51, upon initialization of the IC chip and so on, a command forswitching the pathway of the bypass signal path 36 that is a low-latencypath as described above is issued to the internal logic circuit 32.

In operation S52, path determination is performed by the internal logiccircuit 32. In other words, a switch control signal (switch controlinformation) for the changeover of the switch 34 is generated.

In operation S53, the switch control signal is issued from a switchchangeover controller in the internal logic circuit 32 to the switch 34.

In operation S54, each of the switches 34 receives the switch controlsignal, and switches the coupling of the internal circuit of the switch34, in accordance with the switch control signal. Then, respectiveoperations are put in the waiting state until the switching iscompleted.

In operation S55, upon the completion of the process for the switch 34in S54, a completion signal is issued to the high-speed I/O transceiver33. The high-speed I/O transceiver 33 that received the completionsignal enters the enabled state, and becomes able to transmit/receivethe input/output.

In operation S56, the IC chip enters the operating state and thehigh-speed I/O transceiver 33 starts the data transmission/reception.

(Embodiment 2)

Embodiment 2 is different from embodiment 1, and is an example of a casein which the internal logic circuit is operating at a slower clockfrequency with respect to the signal data rate. For example, in FIG. 6,the data rate per a signal line of the transceiver is 6.4 (Gbit/sec),while the internal logic circuit is operating at a slow clock of 400(MHz).

An IC chip 61 illustrated in FIG. 6 includes an internal logic circuit62, high-speed I/O transceivers 63, Demux/MUX(1:2) units 64, switches65, Demux/MUX(1:16) units 66, a bypass signal path 67, and switchcontrol signal paths 68.

The high-speed I/O transceivers have eight pairs of I/O portsrespectively including four pairs of high-speed I/O transceivers ofwhich data rate is 6.4 (Gbit/sec). The transceiver in the I/O portperforms the exchange of signals with the internal logic circuit ofwhich operating frequency is 6.4 (GHz).

A signal received by the high-speed I/O transceiver 63 is transmitted tothe internal logic circuit 62 via the Demux/MUX(1:2) unit 64, the switch65 and the Demux/MUX(1:16) unit 66. In addition, the data in theinternal logic circuit 62 is transmitted to outside by the high-speedI/O transceiver 63 via the Demux/MUX(1:16) unit 66, the switch 65 andthe Demux/MUX(1:2) unit 64.

A signal received by the receiver of the Demux/MUX (1:16) unit 66 issubjected to serial-parallel conversion by 1:16 demultiplexor: Demux andpassed to the internal logic circuit 62. Meanwhile, data output from theinternal logic circuit 62 is subjected to parallel-serial conversion by16:1 multiplexor: MUX and output from the high-speed I/O transceiver.

The switch 65 and the bypass signal path 67 are provided in themedium-speed signal path in which the frequency of input/output signalshave become 3.2 (GHz) after passing through 1:2/2:1 Demux/MUX. A signalfrom the high-speed transceiver 63 is coupled to other high-speed I/Otransceivers 63 (including its own port) via the bypass signal path 67and the switch 65.

According to the present embodiment, a large-scale logic may beconfigured easily since the clock frequency of the internal logiccircuit may be kept low, and the delay of the bypass signal path 67 andthe switch 65 may be kept small.

(Embodiment 3)

FIG. 7 is a diagram illustrating the configuration of embodiment 3(however, the present example is the one using two transceivers).

In embodiment 3, the clocks of the source/destination thattransmits/receives signals with the high-speed I/O are not necessarilysynchronized completely, and include ones generated from an independentclock source. In order to receive such signals, the receiver of thehigh-speed I/O has a clock recovery circuit to generate a recoveredclock synchronized with the clock at the transmitting side, and uses therecovered clock for receiving signals.

An IC chip 71 illustrated in FIG. 7 includes an internal logic circuit72 and transceivers 73.

The transceiver 73 includes a clock recovery circuit (CRU) 74,demultiplexers 75, 77, a switch 76 (input side), a switch 79 (outputside), multiplexers 78, 710, a switch control signal path 711 and abypass signal path 712.

In the present embodiment, the demultiplexers 75, 77, the switch 76(input side), the switch 79 (output side), the multiplexers 78, 710 aredriven in accordance with a clock recovered by the clock recoverycircuit 74.

According to the above configuration, there is no need to use thesimilar clock in the entire system, increasing the degree of freedom inthe system configuration, and at the similar time, when a receivedsignal is transmitted to the bypass path, the switch and thetransmitter, no delay occurs accompanying the clock switching (FIFO isused generally).

(Embodiment 4)

FIG. 8 is a diagram illustrating the configuration of embodiment 4.Embodiment 4 is a circuit in which in certain high-speed I/O ports, acircuit for correcting a timing mismatch (skew) between a plurality ofsignal lines is included in the bypass signal path.

An IC chip 81 illustrated in FIG. 8 includes an internal logic circuit82, high-speed I/O transceivers 83, switches 84, timing correctioncircuits 85, a clock generation circuit 86, a bypass signal path 87 andswitch control signal paths 88.

The correction of a skew is realized, after performing clock recoveryfor each of a plurality of signals and receiving the signals byperforming timing matching (retiming) with a single clock. When there isa timing mismatch equal to or more than one bit time (1UI) of a signal,the timing matching is performed by a delay circuit including a flipflop. The timing matching in units of one bit time is performed upon thesystem start-up after the power is turned on. The switch 84 transmitsdata and a clock synchronized with the data to the timing correctioncircuit 85. In FIG. 8, the clock generation circuit 86 generates asingle clock to perform the timing matching.

FIG. 9 is a circuit illustrating the configuration of the timingcorrection circuit 85. In FIG. 9, an inter-bit timing correction circuitusing a demultiplexer is explained.

In the timing correction circuit 85, an input for receiving data (#1-#N)from the switch 84 as well as a clock synchronized with the data isprovided. When clocks are recovered on the basis of input data, however,each pieces of data are not synchronized as illustrated in FIG. 10,generating a skew. In other words, a skew occurs even between inputsignals synchronized with clock signals transmitted from a signal sourcehaving the similar clock source. Therefore, the data is input to the 1:2demultiplexer illustrated in FIG. 9 including FFs 91, 92 and 93. Forexample, when input data (#1) “A” is input, data “A” obtained by the 1:2Demuxing of the input data (#1) in FIG. 10 is output to the output ofFFs 92 and 93. In this case, the output data “A” from the FF 92 has adouble data length, and the output data “A” from the FF 93 is outputwith a shift corresponding to one cycle of the synchronous clock. Afterthat, a clock generated by the clock generation circuit 86 is divided byan FF 96 and input to a selector 94, and data is selected alternatingly.After that, synchronization is performed by punching out, by the FF 95,the output of the clock 94 with the clock generated by the clockgeneration circuit 86.

The skew of data output from the switch 84 may be compensated also foreach piece of data (#2-N) by performing the control in the similarmanner as described above.

According to the present embodiment, the influence of the skew between aplurality of signals may be eliminated. For this reason, the applicationof the present embodiment to a back-plane type wiring topology in whicha plurality of signals are transmitted over a middle distance (forexample, 1m) makes it may possible to perform signal transmission inwhich not only the waveform disturbance but also the skew between thesignal lines is compensated.

(Embodiment 5)

FIG. 11 is a diagram illustrating the configuration of embodiment 5. AnIC chip 11 illustrated in FIG. 5 includes an internal logic circuit 112,a high-speed I/O transceiver 113 and switches 118, 119.

The high-speed I/O transceiver 113 includes a demultiplexer 116, amultiplexer 117, a current mode driver 114 and a current mode receiver115.

The present embodiment uses a current mode signal transmission circuitwith a small amplitude for the data path of the bypass signal path(including the switch). The transmission of a current mode signal isperformed by the current mode driver 114 (using a differential pair)with a high output impedance, and the reception of the signal isperformed by a current-voltage conversion circuit (transimpedanceamplifier) with a low input impedance. The current feedback type withwhich the voltage output of the output buffer is converted into acurrent by transconductor amplifier and feeded back to the output nodeis used for the transimpedance amplifier. In addition, the reception isperformed by the current mode receiver 115 via the switches 118, 119.

The switch circuits 118, 119 have a tree structure including an nMOSswitch in the data path. Since the current mode signal transmission isperformed, there is little influence of voltage drop, and since a smallsignal voltage is used to drive a large-capacity internal wiring, thepower consumption is reduced.

(Embodiment 6)

FIG. 12 is a diagram illustrating the configuration of embodiment 6. Inthe embodiments described above, the switch is selectively switched sothat the high-speed signal lines on the board may be coupled one to one,and the propagation delay of signals hopping via the chip is alsominimized. Then, since the signal lines are coupled one to one, there isno multiple reflection of a signal due to the multidrop coupling.

However, there is a case where the similar signal is transmitted to anumber of destinations by one-to-many coupling. Then, when a signal istransmitted to the entire system, one-to-many signal broadcasting may berequired. However, there is a problem that since the one-to-many signalbroadcasting involves a large load capacity, it is difficult tobroadcast a high-speed signal.

In embodiment 6, when transmitting a signal received by a receiver fromoutside the switch to a transmitter via a bypass signal path 129 andswitches 124, 127, the similar signal may be broadcasted to a number ofdestinations by one-to-many coupling.

For example, an internal logic circuit 122 generates a switch controlsignal so that a switch A in FIG. 12 transmits a signal to switches Band C. Then, a switch changeover controller of the internal logiccircuit 122 generates a switch control signal so that the switches B andC select the signal from the switch A.

The switch control signal performs the switching of the correspondingswitches 127(A, B, C) via a switch control signal path 1210, and changesthe coupling to one-to-many.

According to the present embodiment, signals may be transmitted whilesolving the problem described above.

(Embodiment 7)

FIG. 13 is a diagram illustrating the configuration of embodiment 7.According to this embodiment, the delay of a bypass signal path may beselected, and the delay amount of the bypass signal path may be changedrespectively for each signal path.

In the circuit illustrated in FIG. 13A, a function for controlling thedelay amount is provided in the switch 24 in the circuit illustrated inFIG. 2, in addition to the switching function for selecting the path.

A switch 131 illustrated in FIG. 13 includes a path selector 132 and adelay amount controller 133.

The path selector 132 performs switch changeover in accordance with aswitch control signal transmitted from an internal logic circuit 22 viaa switch control signal path 29 upon configuration.

The delay amount controller 133 changes the delay amount in accordancewith a delay amount control signal transmitted from the internal logiccircuit 22 via the switch control signal path 29 upon configuration.

For example, in the case of receiving a 3.2 (GHz) signal and returning asignal from the similar high-speed I/O port, a 1:2, 2:1 processperformed using a multiplexer and a demultiplexer results in a delay of4UI at the minimum in total. Meanwhile, in the case of transmitting asignal to a port on the opposite side with respect to the internal logiccircuit 22, signal processing using 1:4, 4:1 demultiplexer andmultiplexer results in a delay of 16UI. Thus, when the delay amountvaries because of the system configuration, the delay amount is matchedby means of the setting of the delay amount controller 133 in the switch131. The configuration may also be made such that, as a method ofmatching the delay amount, the delay may be selected by inserting a flipflop into the signal path.

Meanwhile, for the delay amount, a delay circuit that changes the delayamount in terms of hardware by switching a plurality of passive elementssuch as the resistor and the capacitor may be used, or a plurality ofbuffer circuits using a desired clock may generate a delay correspondingto the clock. There is no limitation as long as it is a delay circuit.

In addition, there is no particular limitation with regard to thecoupling order of the path selection block 132 and the delay amountcontroller 133.

Next, the control flow illustrated in FIG. 14 is explained.

In operation S141, with the initialization of the IC chip and so on, asetting command for performing the switching of the path of a bypasssignal path 28 that is a low-latency path as described above and theswitching of the delay amount is issued to the internal logic circuit32.

In operation S142, the path determination is performed by the internallogic circuit 22. In other words, a switch control signal (switchcontrol information) for performing the switching of the path for theswitch 131 is generated. In addition, a delay amount control signal(delay amount control information) is generated for determining thedelay amount to be set for each signal path.

In operation S143, the switch control signal is issued from the internallogic circuit 22 to the path selection block 132 of the switch 131.

In operation 144, the delay amount control signal is issued from theinternal logic circuit 22 to the delay amount control block 133 of theswitch 131.

In operation 145, each switch 34 receives the switch control signal, andswitches the coupling of the path selector 132 of the switch 34 inaccordance with the switch control signal, and also changes the delayamount of the delay amount control block 133 in accordance with thedelay amount control signal. Respective operations are put into thewaiting state until these switching processes are completed.

In operation S146, upon the completion of the processes in S143, 144, acompletion signal (enable signal) is issued to the high-speed I/Otransceiver. The high-speed I/O transceiver that received the completionsignal enters the enabled state and becomes able to transmit/receivesignals.

In operation S147, an IC chip 21 enters the operating state, and thehigh-speed I/O transceiver starts the transmission/reception of data.

According to the present embodiment, a short delay may be selected forthe path with which the delay may be shortened, without making the delayamounts of all the signal paths equal, which makes it may possible togive a short delay to a signal, and to improve the overall systemperformance.

(Embodiment 8)

FIG. 15 is a diagram illustrating the configuration of embodiment 8. Itis characterized in that transceivers are provided more than the givennumber, so that even if there is a failure in a transceiver or in asignal path coupled to it, signals may be transmitted by bypassing thefaulty path.

An IC chip illustrated in embodiment 8 is an example in which aredundant circuit is added to the circuit in FIG. 3 illustrated forembodiment 1. In the circuit in FIG. 15, a high speed I/O transceiver151, a switch 152 coupled to the bypass signal path 36 and a switchcontrol signal path 153 are provided as the redundant circuit.

Next, the control flow illustrated in FIG. 16 is explained.

In operation S161, with the initialization of the IC chip and so on, afailure detection command for detecting the faulty part is issued to theinternal logic circuit 32. The command may be issued regularly duringoperation.

In operation 162, a failure detection path (a path for detecting afailure) is determined by the internal logic circuit 32. In other words,a switch control signal (switch control information) is generated forperforming the changeover of the switch 34 to check whether thehigh-speed I/O transceiver 33, the bypass signal path 36, the switchcontrol signal path 35, the switch 34 and so on are operating normally.Furthermore, a circuit for determining the failure detection (failuredetection determination circuit) in the internal logic circuit 32 is putinto the enabled state (being able to make the determination).

Here, in the case of failure detection within the IC chip, failuredetection information for performing switching to the failure detectionpath may be prepared in advance, and the stored failure detectioninformation may be called up upon the reception of a failure detectioncommand, to form the failure detection path. Meanwhile, failuredetection information may be prepared in consideration of the couplingand configuration of another IC chip, to form the failure detectionpath. In other words, the response timing from another IC chip and so onmay be measured to perform the failure detection.

In operation S163, a failure detection signal transmission command isissued from the internal logic circuit 32. At this time, the failuredetection signal transmission command is issued to a correspondinghigh-speed I/O transceiver 33 via the switch 34. For example, thehigh-speed I/O transceiver that received the command makes thetransmitter and the receiver in the high-speed I/O transceiver 33operate to form a loop and to return the data to the internal logiccircuit 32.

In operation S164, the data prepared in advance for identifying thefaulty part is transmitted from the internal logic circuit 32 to thecorresponding high-speed I/O transceiver 33. Then, whether the responseis normal or not is determined by the failure detection determinationcircuit.

In operation S165, whether the process of S164 has been completed forall high-speed I/O transceivers 33 is checked.

In operation S166, when there is a failure according to the aboveoperations, switching is performed so as to avoid the faulty path and touse the redundant circuit.

In operation S167, the IC chip enters the operating state and thehigh-speed I/O transceiver 33 starts the transmission/reception of data.

Thus, the reliability of the entire system may be improved significantlyby adopting the redundant system for signals between chips.

(Embodiment 9)

FIG. 17 is a diagram illustrating the configuration of embodiment 9.Embodiment 9 includes IC chips 171-174. The IC chips 171-174 haveinternal logic circuits 175-178 and low-latency switch parts179-1712(A-D).

The wiring between the respective IC chips 171-174 is done with bypasssignal paths coupling the switch parts 179-1712 (A-D).

The coupling of the bypass signal path is switched by the switch parts179-1712. For the changeover of the switch parts 179-1712, for example,a configuration setting command (coupling information) for themanagement (control and read-out) is generated by an internal logiccircuit 178(D), and issued from the internal logic circuit 178 to therespective switch parts 179-1712 via the bypass signal path.

In this embodiment, there is no signal switch control signal path, andthe configuration setting command is transmitted/received via the bypasssignal path.

With this configuration, IC chips may be coupled with thecompletely-periodical one-to-one coupling since there is no controlsignal and the like except for the bypass signal path coupled betweenthe IC chips, enabling the implementation with little problem of thedegradation of signal quality.

According to the embodiments described above, since the signal lines arecoupled one-to-one, the problem of multiple signal reflection due tomultidrop coupling does not occur. In addition, since there is no signalcrossing part, the problems of crosstalk and impedance mismatching thathappen at a crossing part are suppressed. For these reasons, thetransmission rate may be improved while avoiding the problem of thedegradation of signal quality, improving the overall system performance.

The aforementioned embodiments may be applied to signal transmissionbetween IC chips, between elements and between circuit blocks on an ICchip, and particularly to a technique of high-speed input/output circuitin which a low-latency bypass signal path and switch are provided.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments) of the presentinventions have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. An integrated circuit comprising: an internal logic circuitprocessing data input from one of a plurality of input terminals andoutputs processed data to one of a plurality of output terminals; aplurality of bypass paths bypassing the internal logic circuit; a firstswitch, provided between a first input terminal included in theplurality of input terminals and the internal logic circuit, switchingpathways of a first path used for inputting the data to the internallogic circuit from the first input terminal and a bypass path used forbypassing the internal logic circuit; a second switch, provided betweena first output terminal included in the plurality of output terminalsand the internal logic circuit, switching a pathway of the second pathused for outputting the processed data to the first output terminal fromthe internal logic circuit and the bypass path used for outputting thedata bypassing to the first output terminal; and a timing correctioncircuit correcting a timing mismatch between signals output from each ofthe first switch and the second switch, when an input signalsynchronized with a clock signal is transmitted from a signal sourcehaving a clock source, wherein the internal logic circuit includes aswitch changeover controller performing the functions of selecting atleast one of paths within the logic circuit and the bypass path,generating a switch control signal for the changeover of the firstswitch and the second switch, issuing the switch control signal to thefirst switch and the second switch, entering a waiting state until theswitching of the first switch and the second switch is completed, andissuing a completion signal when the switching of the first switch andthe second switch completes, and wherein, when the input signal is inputfrom the first switch or the second switch to the timing correctioncircuit, the timing correction circuit generates a first output signalhaving a doubled length of the input signal, and a second output signalis shifted from the first output signal by one cycle of the clocksignal, selects the first output signal and the second output signalalternately by using a divided clock of the clock signal, and performscorrection of timing by punching out the selected first or second outputsignal by the clock.
 2. The integrated circuit according to claim 1,wherein serial-parallel conversion is performed for an input signalreceived by a receiver of one of transceivers, the serial-parallelconverted signal being transferred to the bypass signal path configuredwith a path elected by performing the changeover of one of the firstswitch and the second switch by the switch changeover controller;transmitted to a transmitter that is included in the other of thetransceivers; and output after parallel-serial conversion is performed.3. The integrated circuit according to claim 1, further comprising: aclock recovery circuit recovering a clock synchronized with a signal ata receiver side of one of transceivers, wherein when a signal receivedby the receiver is transmitted from a transmitter that is included inthe other of the transceivers via the bypass signal path, thetransmitter operates in synchronization with the recovered clock.
 4. Theintegrated circuit according to claim 1, wherein in case a signalreceived by a receiver is transmitted from a plurality of transmittersthrough the bypass signal path, a changeover of the corresponding one ofthe first switch and the second switch is performed to make aone-to-many configuration.
 5. The integrated circuit according to claim1, wherein at least one of the first switch and the second switchcomprises a delay amount controller changing a delay amount of a signaltransferred through the bypass signal path.
 6. The integrated circuitaccording to claim 1, wherein the plurality of bypass paths exchange,between transceivers, a transfer signal transmitted/received between oneof the transceivers by bypassing the internal logic circuit, thetransceivers are provided more than a given minimum number, and even ifthere is a failure in the transceiver or a signal path coupled to thetransceiver, a signal is transmitted while bypassing a faulty path. 7.The integrated circuit according to claim 1, wherein when a bypasssignal path between the integrated circuits is changed, informationgiven for a changeover of at least one of the first switch and thesecond switch goes through the transceiver.
 8. The integrated circuitaccording to claim 1, wherein in the bypass signal path, transmission isperformed using a small-amplitude signal.
 9. The integrated circuitaccording to claim 1, wherein at least one of the first switch and thesecond switch is a crossbar switch.
 10. The integrated circuit accordingto claim 1, wherein the plurality of bypass paths exchange, betweentransceivers, a transfer signal transmitted/received between one of thetransceivers by bypassing the internal logic circuit.